Posts Tagged ‘Vitis’

Main Characteristics

This is the second article of a series, which aim is a feasibility study for a modular system composed of the main control board based on Xilinx ZYNQ Ultrascale+ and servo satellite motor drives based on Xilinx ZYNQ-7000. The objective of the system is to control a robot composed of multiple joints. The article’s target is an automation of a prostate biopsy to assist doctors during medical procedures. The biopsy is executed by driving one mechanical positioner composed of 6 Permanent Magnet Synchronous Motors (PMSM) motors and multiple joints

Introduction

This article will talk about the Ultrasound Ultrafast Imaging modality on the new AMD-Xilinx Versal chip. The work described here is an implementation by MakarenaLabs for AMD-Xilinx and is currently in early access for customers.

To begin with, we will briefly introduce the UltraFast methodology and what does it mean.

Secondly we are going to talk about Versal and how to create and partition design on this new technology.

Lastly we are going to talk about the Ultrasound Libraries on the new Versal chip and how to exploit them.

UltraFast Imaging

UltraFast Imaging is a

There are two methods for using devices on FPGA for PYNQ: the integrated microprocessor (PS side) and the programmable logic (PL side). In order to maximize the use of the FPGA, this article shows how you can use the programmable logic for common devices such as SPI, I2C and UART.

We have used this flow also for SMART-IO Project. If you have lost the article about SMART-IO, follow this link!

You can find every design in this article as Github project in the MakarenaLabs Github company.

Design with Vivado for PYNQ

In order to create

Pynq is a famous framework that allows programmers to directly work with FPGA using Python language, which is very intuitive, so let’s take a look at it.

When we want to accelerate a specific software portion, it is generally difficult to interface to it correctly, because you have to synchronize the CPU (generally referred to as Process System, PS) to the FPGA part (generally referred to as Programmable Logic, PL). In modern SoCs, we use the “axi” interface to make the two parts communicate, but its Hardware Description Language (HDL) implementation

Introduction

DNNDK allows the productivity in deploying AI inference on Xilinx platforms. In fact, it provides a solution for deep neural network applications. So, in this article we will present the DNNDK tool for the FPGA integration of Deep Neural Network and Convolutional Neural Network.

Artificial Neural Networks

Artificial neural networks (ANN) or connectionist systems are computing systems similar to biological neural networks likes animal brains. In particular, such systems “learn” to perform tasks by considering examples, generally without being programmed with task-specific rules. At this point, you can get it to learn things, recognize

https://www.linkedin.com/pulse/digital-twin-xilinx-alveo-vitis-sps-trade-show-giulio-corradi-1f/

After 30 years of SPS IPC Drives, the trade show changed the name into SPS – smart production solutions reflecting the digital transformation that occurs in automation technology.

Digital Twin (DT) in relation to Cyber-Physical-Systems (CPS) are among the main themes of this digital transformation anticipated by the Industry 4.0 initiative.

According to DirectIndustry e-magazine interview to Sylke Schulz-Metzner, Vice President SPS Mesago Messe Frankfurt GmbH, “digital twins is sure to play a large role this year and in the future at SPS…In the future, it will be as difficult to imagine the world